An essential semiconductor device is semiconductor memory, such as a random access memory (RAM) device. A random access memory device allows the user to execute both read and write operations on its memory cells. Typical examples of RAM devices include dynamic random access memory (DRAM), static random access memory (SRAM), and cache memory.
DRAM is a specific category of RAM containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. The transistor is often referred to as the access transistor or the transfer device of the DRAM cell.
FIG. 1 illustrates a portion of a DRAM memory circuit containing a DRAM cell as a prior art. DRAM cell contains a storage capacitor 114 and an access field effect transistor or transfer device 111. One side of the storage capacitor 114 is connected to a reference voltage 116. The other side of the storage capacitor 114 is connected to the drain of the transfer device. The gate of the transfer device is connected to a signal known in the art as a word line 112. The source of the transfer device is connected to a signal known in the art as a bit line 113. With the memory cell components connected in this manner, it is apparent that the word line 112 controls access to the storage capacitor 114 by allowing or preventing the signal (representing data “1” or data “0”) carried on the bit line 113 to be written to or read from the storage capacitor 114. Thus, DRAM cell contains one bit of data (i.e., data “1” or data “0”). In these days, DRAM has progressed its miniaturization and as a result there arises difficulties in obtaining necessary capacitance, in decreasing leakage current at turn-off of access transistor, and in holding data charge. Moreover, many supply voltages are required for controlling DRAM cell, such as the reference voltage of storage capacitor 116 is usually connected to half VDD where VDD is high level of memory array, which half VDD is internally generated. The pre-charge level of bit line is half VDD. High level of word line is VPP which is higher than VDD, and internally generated in most applications. The body of transfer gate 115 has VBB which is negative and internally generated. Internal voltage generators need more debugging, optimizing. And those generators consume more power and increase die area.
In FIG. 2, one of the prior art, “High density planar SRAM cell using bipolar latch-up and gated diode breakdown”, U.S. Pat. No. 6,104,045 is illustrated. It involves the interconnection of two memory cells so that they share a common p-n-p emitter. Each bipolar transistor device 221 and 221′ comprise two complementary bipolar transistor 222 and 222′ connected with base 224 and 224′ to form gated diode 223 and 223′. Row address line 230 is connected to the emitters of transistor 222 and 222′, respectively, while column address line 232 and 232′ are connected to the emitters of transistor 221 and 221′. Write row address line 231 is connected to the gate 226 and 226′ of the gated diode 223 and 223′.
To write data “0”, that is, turn-off diode, word line and bit line have same voltage which makes turn-off diode. It sustains turn-off state of diode 221 in FIG. 2 by introducing a pulsed gate bias, which couples the base 224 of transistor 221, and the base 225 of transistor 222. As the base 224 goes up, the diode 221 turns off because the voltage is less than forward bias between column line 232 and the base 224, while the base 225 turns on transistor 222. The turn-off state is sustained by the base 224 when pulse moves from ground to high level.
To write data “1”, that is, turn-on diode, an external stimulus such as a base current must be induced by avalanche multiplication. Base current can be generated by introducing a pulsed gate bias and higher base voltage that initiates current multiplication in the gated diode when word line 230 is at ground level and bit line 232 is at high level. The pulse level must be calculated to yield sufficient current so that the sum of the common base current gains, .alpha..sub.1 and .alpha..sub.2, of bipolar transistors 221, 221′, 222 and 222′ exceeds one. The bias applied to induce latch-up is “pulsed” in the sense that it is only applied to initiate latch-up. As shown in FIG. 3, the cell is stable in the latched-up condition as a result of the pulse-initiated latch-up, which occurs during write operation to store data “1”. In order to sustain latched data “1” during standby, holding current is supplied, which is less than that of active mode in FIG. 3. Disadvantages are that the holding current is too high for all memory cells even though each memory cell has very little current, and relatively high voltage is required to make avalanche multiplication.
In FIG. 4, another prior art of memory cell is illustrated, that is U.S. Pat. No. 6,229,161 “Semiconductor capacitively-coupled negative differential resistance device and its applications in high-density high-speed memories and in power switches”. This is directed to a negative differential resistance device that uses a capacitively-coupled gate adjacent to the negative differential resistance device. The cell consists of two elements: a negative differential resistance device 430 and an NMOS access transistor 434 as shown in FIG. 4. The access transistor 434 includes a gate 436 that forms part of a first word line and n+ drain and source regions, with one of the n+ drain and source regions connected to a bit line 441. The device 430 has a middle p-region adjacent to a charge plate, or gate-like device 435. The charge plate 435 forms part of a second word line and is used to enhance switching between the cell's two stable states: the off state, where the device 430 is in a current-blocking mode; and the on state, where the device 430 is in a current-passing mode. The voltage of the storage node 439 is at its high value for the on state, and the holding current of the negative differential resistance device 430 is provided by the subthreshold current of the access transistor 434. The speed of negative differential resistance based memory achieved about 2 ns to 5 ns, as published.
One of disadvantage is that the charge plate 435 should be negative bias voltage during standby. Second word line 437 has very high switching current, which signal stays at negative level to store data during standby, then moves from negative to high level to write cells, and consequently consumes high power with internal negative voltage generator. Moreover, this prior part of memory cell in FIG. 4 has one more disadvantage to sustain latched-up data by subthreshold current, if holding current is higher than subthreshold current, memory cell loses data. In FIG. 5 the current-voltage curve is illustrated. This prior art of memory cell is refreshed by periodic accessing with short pulse which is described in “Fully planar 0.562/spl mu/n/sup 2/T-RAM cell in a 130 nm SOI CMOS logic technology for high-density high-performance SRAMs”, IEDM 2004, but periodic accessing needs switching current and more control circuits.
In FIG. 6 one more prior art illustrates “Merged MOS-bipolar capacitor gain cell”, U.S. Pat. Nos. 6,940,761, 6,943,083. Read word line 652 is connected to gate 653. The write word line 657 is operable to bias the base region function of the bipolar device of the merged MOS-bipolar structure. Thus, as shown in FIG. 6, the merged device consists of a MOS (Metal-Oxide Semiconductor) transistor-bipolar transistor-storage capacitor. The sense device used to read the cell is the PMOS transistor 653 which is addressed by the read word line 652.
In operation, if negative charge or electrons are stored on the body 654, then the body will be slightly forward biased and the PMOS transistor 653 will be more conductive than normal. Charge is injected on to the floating body 654 of the PMOS transistor 653 by the n-p-n vertical bipolar transistor 658. Forward bias can be achieved by driving the emitter/sourceline 659 negative and by driving the write data word line 657, connected to the base/source region 660, positive to achieve a coincident address at one location. The cell can be erased by driving the drain 651 positive and by driving the gate 652 negative to forward bias the drain-body p-n junction. However, this prior art of cell needs complexity of operation using negative voltage, and needs MOS device to read which is more complicated to shrink.
And other prior arts are published as follows, Tanaka et al, “Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM”, Electron Devices Meeting, 2004 IEDM Technical Digest. December 2004, and Shino et al, “Operation voltage dependence of memory cell characteristics in fully depleted floating-body cell”, IEEE Transactions on Electron Devices, vol. 52, No. 10, pp 2220–2226, October 2005. These types of memories are so-called, “gain-cell”, or “floating-body cell”. However, these cells need negative voltage for read and write operations, and write time is relatively slow to generate ions by impact ionization, which takes 5 ns to 10 ns, as published.
Still, there is a need in the art for a memory circuit and cell for random access memory devices, which realize low power, high density and simple structure to fabricate on the wafer. In the conventional MOS access transistor as shown in FIG. 1, there is a parasitic n-p-n bipolar transistor wherein the body 115 serves as the base, source/drain serve as the emitter/collector. During read and write cycle, the base (body) 115 is at ground (or negative) to prevent bipolar effect. The parasitic bipolar transistor is not wanted device in the conventional memories which is usually turned off, but now adding one more terminal to the parasitic bipolar transistor in the conventional memory, a p-n-p-n diode (or n-p-n-p) can serve as four-terminal diode access device for the next generation memory devices with good performance and simple structure. Separately, storage element is required to store data such as a capacitor for the capacitor memory, but there is no need of high capacitance because the storage capacitor only drives the base of bipolar transistor while strong diode drives heavy bit line.